Recent Advancements in TSMC Packaging Technology

In addition to its semiconductor technology, TSMC has emerged as a pioneer in IC packaging technology. Recognizing the complexity of heterogeneous system-level integration with multiple chiplets into single package is as crucial as transistor level advancements. TSMC has developed 3DFabric® platform which is a comprehensive family of 3D die stacking and packaging solutions. The TSMC 3DFabric® provides a holistic packaging design using integrated multi-die systems. It offers 3D silicon stacking and several advanced packaging technologies. Packaging technologies such as Chip on Wafer on Substrate (CoWoS), Integrated Fan-Out (InFO), and System on Integrated Chips (SoIC) are offered to TSMC customers. What sets TSMC apart is not just those unique packaging solutions, but the ability to combine them in a single package. For example, in a multi-chiplet logic-memory system, a CoWoS technology is used for the logic dies, but 3D SoIC is used to stack multi memory dies and then redistributing signals through InFO layers. All are assembled within the same package. This holistic approach enables system architects to design complex systems using system-in-package (SIP) technology. 

1. CoWoS Packaging Technology: The CoWoS is TSMC’s 2.5D packaging technology in which it places multiple dies (chiplets) side by side on a large silicon interposer. The interposer is then placed on the substrate which is connected to the external PCB. CoWoS TMSC is divided into three types that are standard (CoWoS-S), redistribution layer (CoWoS-R) and local (CoWoS-L). 

Standard CoWoS-S: In the case of the standard CoWoS-S, the dies are flipped and connected to the interposer using micro-bumps. The micro-bumps are fine scale soldering bumps that connects the die pads to the interposer. The interposer provides ultra-dense and short interconnect wiring, thus allowing for massive bandwidth between dies. This interposer acts as a high-density wiring layer that interconnects the dies with extremely short and fine-pitch signal paths. We may consider the interposer acts as a mini motherboard within the package that connects multi-dies together. The interposer is made of silicon that is fabricated using already matured semiconductor processes to provides micrometer-scale high density metal traces for routing with excellent signal integrity. Through Silicon Via (TSV) is used to connect through the interposer. The entire interposer assembly is then mounted onto an organic substrate using C4 Cu bond-bumps.  This allows data to move between the logic die and memory stacks with ultra-high bandwidth and low latency. The substrate provides a distribution to the large power signals and the IO signals from the interposer to the external soldering balls. 

Redistribution Layer CoWoS-R: The CoWoS-R has the interposer acts as a redistribution layer (RDL). The RDL serves as interconnect network that links the embedded dies (or chiplets), active logic dies, and high-bandwidth memory (HBM) stacks into a unified electrical system. While the interposer provides mechanical scalability, the RDL determines signal integrity, bandwidth density, and electrical performance. The RDL formation begins after the silicon interposer segments are embedded and the reconstituted wafer surface is planarized to achieve nanometer-scale uniformity. This flatness is essential to ensure tight line width and spacing control across the wafer. The RDL acts as far more than a passive interconnect; it is an active, engineered platform that unites high-density wiring, mechanical reliability, and thermal functionality into one multilayer system.

Electrically, the RDL network handles both high-speed signal routing and robust power delivery. Differential signal pairs and high-speed buses are routed with controlled impedance traces, and TSMC’s design rules specify strict limits on the line width variation, via density, and return path continuity to minimize signal skew and crosstalk. 

The fabrication process includes dielectric spin coating, photolithographic patterning, via etching, seed layer sputtering, electroplating of copper, and final passivation. Modern RDL structures achieve line/space dimensions below 2 µm. To maintain such precision over large wafer diameters, advanced stepper lithography or laser direct imaging is used that are coupled with real-time alignment systems to correct die shift during exposure. Copper thickness typically ranges from 2 to 5 µm per layer, optimized for both current-carrying capacity and minimal resistance-capacitance (RC) delay. Multiple RDL layers—often three or more—are stacked vertically, separated by polymer dielectric films and connected through copper-filled microvias. 

Localized CoWoS-L: The CoWoS-L bridges the gap between the standard CoWoS-S with a full interposer approach and the redistribution CoWoS-R. CoWoS-L employs a localized RDL instead of a full-sized silicon interposer. The localized RDL is placed where massive interconnect with high bandwidth is needed and lower cost and larger die sizes by. It uses RDL only where fine-pitch routing is essential—directly beneath logic dies and HBM stacks—while delegating coarse-pitch routing to an organic substrate or large build-up RDL layers. Unlike a full CoWoS-S interposer that spans the entire package, the localized approach minimizes silicon area, thereby reducing cost and improving warpage control during assembly. In essence, CoWoS-L represents a strategic synthesis of silicon precision and organic scalability. By localizing high-density interconnect regions only where they are needed.

The thin-film localized RDL layers are formed using advanced photolithographic patterning and electroplated copper metallization, similar to wafer-level BEOL processes. Polyimide or PBO dielectric films are spin-coated between metal layers, providing low-k insulation and mechanical compliance. TSMC addresses this by implementing Through-Bridge Vias (TBVs) or Through-Silicon Vias (TSVs) within the local interposer, combined with copper pillars or micro-bumps that interface to the substrate’s build-up RDL. The transition zone between the local RDL and organic substrate is co-designed with electromagnetic simulation to minimize parasitic inductance and reflection, preserving high-frequency performance up to multi-GHz signaling regimes.

TSMC Through-Silicon Via (TSV) Technology: At the heart of 2.5D/3D system integration lies the Through-Silicon Via (TSV) technology—a vertical interconnect structure that enables signals and power to pass directly through the silicon die. TSVs are the vertical spine of silicon layers to allow vertical interconnects through bulk silicon. TSVs are used in CoWoS-S and SoIC technology, while other variants like (TMVs, TBVs) or hybrid bonding are used in CoWoS-R and CoWoS-L. TSVs allow multiple chips to be stacked with extremely short interconnect paths, reducing latency and power consumption while dramatically improving bandwidth density. This 3D stacking approach contrasts with traditional 2D packaging, where dies communicate laterally through organic substrates. The TSVs, typically filled with copper and surrounded by insulating liners, must be fabricated with nanometer precision to ensure reliability, minimal parasitic capacitance, and mechanical stability. However, challenges such as wafer thinning, via alignment, and thermal stress management remain key engineering bottlenecks. 

2. TSMC InFO Packaging Technology: The integrated fan out chip (InFO) is another TSMC packaging solution as part of the TSMC 3DFabric™. InFO is a wafer-level system integration technology that provides a high-density RDL and Through-InFO Vias (TIVs) for high-density interconnect. InFO offers 2.5D and 3D options optimized for specific applications. The InFO package-on-package (InFO-PoP) is the first 3D wafer-level fan-out package, features a high-density RDL and TIVs. InFO-PoP is mostly used in integrating mobile application processors with DRAM. InFO-PoP has better electrical and thermal performance, and a thinner profile than flip chip package-on-package, because it has no organic substrate or C4 bump. InFO on substrate (InFO-oS) is another version of InFO that leverages InFO technology with higher density redistribution interconnection (RDL). 

3. TSMC SoIC Packaging Technology: As HPC and AI systems continue to demand higher bandwidth, power efficiency, and functional density, the semiconductor industry has turned into a 3D packaging innovation. While 2.5D packaging such as TSMC’s CoWoS have revolutionized side-by-side multi-chiplet integration, TSMC SoIC improved the memory-logic integration by stacking multiple active dies vertically, thus forming a true 3D multi-chiplet integration. The TSMC SoIC stacking technology enables die-to-die or wafer-to-wafer bonding with hybrid interconnects. The die-to-die stacks multiple dies vertically, and the wafer-to-wafer stacks the whole wafer vertically. Unlike traditional methods that rely on solder bumps or micro-pillars, SoIC uses direct copper-to-copper (Cu-Cu) bonding combined with dielectric-to-dielectric (oxide-to-oxide) interfaces and thin TSVs. This hybrid bonding approach dramatically shortens interconnect length down to a few micrometers, hence offering extremely low resistance, minimal parasitic capacitance, and unprecedented bandwidth density. The result is near-monolithic performance, where stacked dies behave almost as if they were a single, unified chip.

Structurally, SoIC consists of multiple thinned dies precisely aligned and bonded on top of one another. Each die contains its own active circuitry, power grids, and redistribution layers (RDLs). Once bonded, vertical interconnects are formed by copper vias and hybrid bonds. This creates thousands of high-speed connections between layers. The bottom die, often a high-performance logic processor, is connected to the package substrate through traditional flip-chip or CoWoS interfaces, while upper dies can include additional logic, SRAM, analog, or memory units. This fine-grained vertical integration enables heterogeneous stacking—mixing different process nodes and functions in one compact system. 

One key strength of SoIC lies in its integration flexibility. It is designed to work seamlessly with other elements of TSMC’s 3DFabric ecosystem, which includes CoWoS for 2.5D integration and InFO packaging. For example, a high-performance AI chip might use SoIC for vertical logic-memory stacking, mounted on a CoWoS interposer that connects to multiple stacks of HBM, thus combining the strengths of both 2.5D and 3D approaches in one unified architecture. By bringing monolithic-like performance to multi-die systems, SoIC sets the stage for the next evolution in system scaling—beyond the limits of transistor miniaturization. It allows designers to co-integrate compute, memory, analog, and I/O functions with unmatched interconnect density, all within a smaller footprint and lower power envelope. 

Roadmap and Competitors: While TSMC stands at the forefront of advanced packaging, the race to define the future of semiconductor integration has become a global competition among the industry’s largest foundries and IDMs. TSMC’s roadmap extends through its 3DFabric platform its proven CoWoS packaging solution toward ever-larger silicon interposers that can support eight or more HBM stacks. In parallel, the company’s SoIC-X initiative is pushing 3D stacking to new limits, enabling denser hybrid-bonded vertical integration for logic-on-logic and logic-on-memory systems. 

TSMC is not alone in this race. Intel has made great progress with its Embedded Multi-die Interconnect Bridge (EMIB) technology, which embeds small silicon bridges within an organic substrate to achieve 2.5D integration without requiring a full interposer. Building on this, Intel’s Foveros architecture delivers true 3D stacking by deploying Meteor Lake processors, combining compute, graphics, and I/O tiles into a single compact package. Meanwhile, Samsung’s I-Cube technology is a direct competitor to TSMC’s CoWoS is used on Samsung HBM. Also, Samsung X-Cube 3D stacking solution focuses on logic-memory coupling for AI and HPC. The broader trend is unmistakable: packaging has evolved from a back-end process into a front-line differentiator. 

Summary: TSMC has emerged as an advanced IC packaging company in addition to its transistor technology scaling. TSMC 3DFabric™ platform provides multiple 2.5D/3D packaging solutions such as CoWoS, InFO and SoIC. Those technologies allow for multi-chiplets (multi-dies) to be integrated on a single package.  CoWoS integrates multiple chiplets over interposer making them act as a single monolithic chip. The SoIC allows for 3D homogeneous/heterogeneous stacking making 3D HBM stacked as a single module and be integrated over 3D heterogeneous SOC chiplets. In this article, we also presented an brief overview of traditional packaging technologies which have led to TSMC packaging technology. The lead frame in traditional packaging suffers for RLC parasitics due to the wire bond and lead frame. This has led to substrate-based packaging which either used wire bond or soldering bumps technologies. TSMC provides multi-chiplet packaging technology, which optimizes performance and costs of complex system integration in a single package.